targets/efinix_ti60: use common HyperRAM integration - #770
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Replace the target-local Wishbone slave, L2 cache, and HyperRAM wiring with SoC.add_hyperram(). Preserve the 32MB main RAM mapping, 16KB cache, variable latency, 2:1 clock ratio, and phase-shifted input sampling.\n\nThis depends on LiteX commit 6365b2f6c (soc: add optional L2 cache to HyperRAM integration).
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CI note: the PR-event inventory failure is inherited from current |
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Summary
SoC.add_hyperram()sys2x_psinput samplingThis removes 32 lines of target-specific integration code.
Dependency
Validation
--with-hyperram --build --no-compileCONFIG_L2_SIZEare unchangedEfinity 2025.1 reports the existing
sys2x_ps_pll0_clk:PHASE_SHIFTdesign-check diagnostic for the 315-degree sampling clock in both the previous and new implementations. This migration does not change that clocking configuration.